1. Field of the Invention
The present invention concerns synchronous bus operation for systems such as processors, and more particularly concerns dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus.
2. Related Art
An issue in the present invention concerns energy consumption of integrated circuitry. It is desirable in some circumstances to lower operating voltage of integrated circuitry because this has a great impact on energy consumption. In general, energy consumption of integrated circuitry is proportional to operating voltage squared. Energy consumption is of increasing importance for circuitry of embedded processors because these processors are often used in portable devices such as personal digital assistants, and these devices are increasingly being used for applications which require greater processing power. These applications include audio playback and graphics rendering, such as for browsing the Internet. It is a side effect, however, of lowering operating voltage that operating frequency is also lowered, although not by as much as energy consumption. For example, cutting operating voltage in half general reduces energy consumption by a factor of four and only reduces operating frequency by a factor of approximately two.
Driven in part by the need for higher performance of embedded controllers applied in portable devices with relatively modest power consumption, there have recently been improvements in the capability for quickly reducing the operating voltage of integrated circuitry, which leads to a need for increased flexibility in operating frequency.
Another issue that's dealt with in the present invention concerns tradeoffs that exist in the design of new systems and the reuse of existing system designs. That is to say, the process of designing embedded controllers generally provides a great deal of opportunity for improvement of overall system performance by improving operating frequency of the processor. However, it generally requires a substantial design effort to increase operating frequency of the subsystems. Consequently there's a certain dynamic at work in system design according to which it would be desirable to redesign some subsystems for a higher operating frequency, particularly the processor, while at the same time reusing at least some old subsystem designs without upgrading the operating frequency of the reused designs. However, this presents a problem, particularly in the case of synchronous buses.
It is conventional to use synchronous buses for embedded processors, such as in the case of the IBM “CoreConnect” bus architecture. (“CoreConnect” is a trademark of IBM Corporation.) Aspects of this bus architecture are described in a white paper, “The CoreConnect Bus Architecture,” http://www-3.ibm.com/chips/products/coreconnect, which is hereby incorporated herein by reference. In this architecture, a processor local-bus (“PLB”) and a on-chip peripheral bus (“OPB”) on an embedded controller are both synchronous buses, according to which devices connected to one or the other of the buses operate in synchronism with a clock signal transmitted on the bus.
Referring now to FIG. 1, devices connected to a conventional OPB 110 are illustrated in a high level view, according to the prior art. A clk 120 signal is provided from an outside source to devices on the OPB 110, including those illustrated, namely an OPB arbiter 130, a first OPB master 140.1, a second OPB master 140.2, and an OPB slave 150.1, and the devices 130, 140.1, etc. run at the same frequency, regulated by clk 120.
In the design of a system with synchronous buses it is problematic to redesign a subsystem to operate at a higher frequency, because according to the current state of the art the synchronous buses in the system need to operate at a frequency that is high enough to be compatible with the highest frequency subsystem, and consequently the redesign of one subsystem requires upgrading all the subsystems connected to the synchronous buses to operate at a higher frequency.
For the above reasons, a need exists to improve flexibility of operating frequency on a synchronous bus.